IPSJ-TS      情報処理学会 試行標準 IPSJ-TS 0015:2015
                    Information Processing Society of Japan - Trial Standard  IPSJ-TS 0015:2015

エラー訂正機能付き高信頼伝送路符号 4b/10b

Dependable Line Code with Error Correction Capability: 4b/10b

Publication of version 1 (this version)2015-09-07
Publication of version 2--
Publication of version 3--

Cor.1 to this version--
Comment to TS desk of IPSJ/ITSCJ

Copyright©2015 IPSJ/ITSCJ, All Right Reserved.


Foreword (in Japanese)
0. Introduction
1. Scope
2. Normative references
3. Terms and definitions
4. 4b10b line code

Annex A (informative) Real-time scheduling
Annex B (informative) Characteristics of embedded clock
Annex C (informative) Characteristics of DC balance
Annex D (informative) Implementation of a decoder

Patent Statement

The IPSJ draws attention to the fact that it is claimed that compliance with this Trial Standard may involve the use of patents concerning Japanese patent application No. 2012-14181.

The IPSJ takes no position concerning the evidence, validity and scope of this patent right. The holder of this putative patent right has assured the IPSJ that it is willing to negotiate licences under reasonable and non-discriminatory terms and conditions with applicants throughout the world. In this respect, the statement of the holder of the putative patent rights is registered with the IPSJ. Information may be obtained from:

Faculty of Science and Technology, Keio University
3-14-1, Hiyoshi, Kouhoku-ku, Yokohama, Kanagawa 223-8522, Japan.

Attention is drawn to the possibility that some of the elements of this Trial Standard may be the subject of patent rights other than those identified above. The IPSJ shall not be held responsible for identifying any or all such patent rights.